A recent advanced communication system, for example, requires a higher resolution and accuracy clock signal uniformly used in communication networks and systems. In particular, a digital communication network, a data communication network including mobile communication networks and TV broadcasting networks, and an environmental observation network of global scale require high resolution and stability clock signal.
An example of conventional frequency standard generator to be used for such purposes is shown in the U.S. Pat. No. 5,629,649 issued to Ujiie which is briefly shown in FIG. 6. In this conventional example, the frequency standard generator has a voltage controlled quartz-crystal oscillator which is phase locked to a GPS (Global Positioning System) satellite time signal. The standard generator receives the radio waves from the GPS satellite to reproduce a high accuracy time signal in the radio waves. The time signal in the radio wave is originated by an ultra-high accuracy atomic frequency standard installed in the GPS satellite. The frequency standard generator of FIG. 6 synchronizes the quartz-crystal oscillator with the time signal on the basis of average phase data indicating a phase difference of a long time period between the GPS time signal and the reference clock time of the quartz-crystal oscillator by means of a phase lock loop.
The conventional frequency standard generator of FIG. 6 includes a voltage controlled crystal oscillator (VCXO) 10, a temperature sensor 29 attached to the crystal oscillator 10, a satellite wave receiver 11, a time interval measuring circuit 12, a frequency control processor 13, a D/A (digital to analog) converter, a frequency divider 15 and a frequency converters 16 and 17. An output frequency f.sub.out of the frequency standard generator is used as a standard frequency signal.
The frequency standard generator of FIG. 6 forms a phase lock loop wherein the output frequency of the voltage controlled crystal oscillator 10 is phase locked to the GPS time signal from the GPS satellite. To accomplish the phase lock operation, the output frequency of the crystal oscillator 10 is fedback to be compared with the GPS time signal. A resultant comparison signal forms a control signal to control the phase of the crystal oscillator output to be equal to the satellite time signal. Thus, a negative feedback loop is created to form the phase lock loop noted above as described in more detail below.
More specifically, the voltage controlled crystal oscillator 10 of FIG. 1 includes a quartz-crystal oscillator which has, for example, frequency stability of 5.times.10.sup.-10 /day and a variable frequency range (.DELTA.f/f) of 2.times.10.sup.-7. The quartz-crystal oscillator is preferably provided in a constant temperature oven. The temperature of the oven is monitored by the temperature sensor 29 to feedback control the temperature of the crystal oscillator 10 thereby minimizing the frequency change caused by the temperature change.
The satellite wave receiver 11 receives the radio wave from a GPS (Global Positioning System) satellite and reproduces a time signal in the radio wave. Typically, the time signal from the GPS satellite is a 1 pps (one pulse per second) signal which is modulated by a carrier signal of the radio wave. The time signal in the radio wave is produced by an atomic frequency standard such as a cesium or rubidium frequency standard and has a very high frequency accuracy and stability.
The time interval measuring circuit 12 measures the time interval of the satellite time signal S.sub.1pps from the satellite wave receiver 11 and a crystal time signal V.sub.1pps from the voltage controlled crystal oscillator 10 through the divider 15 to compare the phase difference between the two. Namely, the time interval measuring circuit 12 functions as a phase comparator for the phase lock loop. Preferably, the time interval measuring circuit 12 measures the time interval (phase difference) with higher resolution than the smallest time period of a clock signal used in the circuit by incorporating an interpolation technique (not shown) as is well known in the art.
The frequency control processor 13 receives phase comparison (difference) data from the time interval measuring circuit 12 and produces a phase (frequency) control signal representing the phase difference. The frequency control processor 13 also produces various phase lock parameters which determines a response characteristics of the phase lock loop such as a loop gain and a loop bandwidth. The frequency control processor 13 dynamically determines the frequency control signal and the phase lock parameters based on the phase difference between the satellite time signal S.sub.1pps and the crystal time signal V.sub.1pps.
The D/A converter 14 receives the frequency control signal from the frequency control processor 13 and converts the frequency control signal to an analog voltage which is supplied to the voltage controlled crystal oscillator 10. The output of the crystal oscillator 10 is fedback to the time interval measuring circuit 12 through the divider 15. The dividing ratio of the divider 15 is determined so as to produce a 1 pps pulse rate from the output of crystal oscillator 10 to be supplied to the time interval measuring circuit 12.
In this example, the output of the crystal oscillator 10 is also used as a clock signal for the time interval measuring circuit 12 through the frequency converter 16 which is typically a frequency multiplier to form a clock signal whose frequency is high enough to obtain a required level of resolution in measuring the time interval by the time interval measuring circuit 12.
In the frequency control processor 13, a frequency control algorithm is so established that the phase lock loop is not influenced by interference signals accidentally or intentionally applied to the radio wave. Such interference signals may last for several hundred seconds. Thus, the frequency control algorithm by the frequency control processor 13 includes a digital filter having a very long time constant such as one thousand seconds so that the phase lock loop response is not affected by the interference signals.
In this conventional technology, however, there arises a case in which phase difference data T.sub.id of FIG. 6 indicating the phase difference between the generated standard frequency through the divider 15 and the input time signal S.sub.1pps received from the satellite will not converge to zero. Alternatively, it takes a very long time for the phase difference data to reach zero. This situation is cased by various factors including the interference signals noted above, changes in the environment temperature, and the like. Another reason is that the phase lock loop of FIG. 6 functions to converge the frequency difference rather than the phase difference to zero.
Some applications of a frequency standard generator such as a mobile communication system using CDMA (Code Division Multiple Access) requires the phase of a frequency standard be within a predetermined difference from that of the GPS time signal. Although the conventional frequency standard generator is capable of generating a high stability and accuracy reference frequency, it tends to be unable to reach within a desired range of phase difference relative to the phase of the GPS time signal. Alternatively, in the conventional technology, it takes too long a time, such as several hours, to decrease the phase difference within a desired range because of the large time constant associated in the phase lock loop.